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ATmega128
Idle Mode
ADC Noise
Reduction Mode
Power-down Mode
Power-save Mode
W hen the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial
Interface, Timer/Counters, W atchdog, and the interrupt system to continue operating. This sleep
mode basically halts clk CPU and clk FLASH , while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the
Analog Comparator interrupt is not required, the Analog Comparator can be powered down by
setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will
reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-
cally when this mode is entered.
W hen the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, the External Interrupts, the
Two-wire Serial Interface address watch, Timer/Counter0 and the W atchdog to continue
operating (if enabled). This sleep mode basically halts clk I/O , clk CPU , and clk FLASH , while allowing
the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the
ADC Conversion Complete interrupt, only an External Reset, a W atchdog Reset, a Brown-out
Reset, a Two-wire Serial Interface address match interrupt, a Timer/Counter0 interrupt, an
SPM/EEPROM ready interrupt, an External Level Interrupt on INT7:4, or an External Interrupt on
INT3:0 can wake up the MCU from ADC Noise Reduction mode.
W hen the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-
down mode. In this mode, the External Oscillator is stopped, while the External Interrupts, the
Two-wire Serial Interface address watch, and the W atchdog continue operating (if enabled).
Only an External Reset, a W atchdog Reset, a Brown-out Reset, a Two-wire Serial Interface
address match interrupt, an External Level Interrupt on INT7:4, or an External Interrupt on
INT3:0 can wake up the MCU. This sleep mode basically halts all generated clocks, allowing
operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 89
for details.
W hen waking up from Power-down mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined by the same CKSEL fuses that define the
Reset Time-out period, as described in “Clock Sources” on page 36 .
W hen the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-
save mode. This mode is identical to Power-down, with one exception:
If Timer/Counter0 is clocked asynchronously, i.e., the AS0 bit in ASSR is set, Timer/Counter0
will run during sleep. The device can wake up from either Timer Overflow or Output Compare
event from Timer/Counter0 if the corresponding Timer/Counter0 interrupt enable bits are set in
TIMSK, and the global interrupt enable bit in SREG is set.
If the Asynchronous Timer is NOT clocked asynchronously, Power-down mode is recommended
instead of Power-save mode because the contents of the registers in the asynchronous timer
should be considered undefined after wake-up in Power-save mode if AS0 is 0.
This sleep mode basically halts all clocks except clk ASY , allowing operation only of asynchronous
modules, including Timer/Counter0 if clocked asynchronously.
45
2467X–AVR–06/11
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